Chip design usually only moves forward. You lock in the floorplan and RTL early, and while technically you can go back later, it is manual and painful, so in practice teams rarely do. When backend design turns up problems, such as congestion, timing, IR drop violations that are difficult to close, fixing them for real would mean unwinding decisions made stages ago. So people just patch around it instead. The insight comes too late.
Congestion hotspots found during place and route often trace straight back to a macro placement or hierarchy call made at floorplan. Feed that pattern forward and the floorplan sidesteps the hotspot instead of routing around it later.
Timing-critical paths that keep reappearing at signoff often point to a pipelining or partitioning decision back at RTL. If the backend flags the same logic cone cycle after cycle, that's RTL's problem to restructure, not something PD should keep re-optimizing forever.
IR drop and thermal hotspots are shaped largely by power grid choices made at floorplan time. Signoff sees the failure; floorplanning owns the fix. Connect the two and a signoff violation becomes a floorplan constraint.
It's the same thing we keep bumping into with agentic flows: the data exists, it's just stuck downstream, cut off from the stage that could act on it. An agent needs a unified cross-domain view to decide well in the moment; a team needs that view stretched across iterations and across projects, so the same class of bug doesn't get rediscovered at signoff every single time.
We're not mainly interested in closing the backend faster, though nobody would complain if it happened. What we'd really like to see is signoff data flowing back to make the floorplan and the RTL better.